Channel-Length Independent Electrical Characteristics of Oxide Thin-Film Transistors

Adapted from [1]

Introduction

Multi-component metal oxide thin film transistors (TFTs) including InGaZnO (IGZO) have gained popularity as a replacement for conventional Si-based TFTs due to their superior electrical properties, transparency, and large-area applicability. However, a gap still exists between emerging oxide and conventional Si-based TFTs in terms of field effect mobility (μ_FE), stability, and process immunity, which limit the widespread commercialization of oxide TFTs. To expand oxide TFT technology for broader applications, there is a high demand for short-channel capability, which can boost the driving current, increase integration density, reduce the dead area, and enhance productivity, among others. Besides, it is necessary to enable low leakage current in the scaled device.

To retain the advantages of a low leakage current in the short channel, careful control of the threshold voltage (V_t_h) is necessary, and operation in the enhancement mode is preferred. However, the well-known short-channel effects such as "hot carrier", drain-induced barrier lowering (DIBL), and reduced channel resistance can cause inconsistent electrical characteristics as the channel length (L_CH) is shortened. Typically, oxide TFTs reported to date have L_CH values of a few μm, limited by the photolithography process in large-area fabrication. It is common for V_t_h to shift negatively as L_CH decreases, particularly for L_CH values below 5 μm. This behavior reflects not only the above short-channel effects, but also defects attributable to impurities. This undesired behavior can be attributed to the lateral diffusion of carriers and impurities during the device integration process, which leads to the shortening of the effective channel length. Since the diffusion length is around a few micrometers, it is easy to attain the negative shift of V_t_h for TFTs with L_CH shorter than 5 μm.

Herein, we propose a commercially favorable method using conventional SiO_x to improve the back interface of IGZO TFTs and the short-channel capabilities.

Figure 1. a) Schematic of the fabrication process (gate to source/drain (S/D)... — Figure 1. a) Schematic of the fabrication process (gate to source/drain (S/D) formation), and b) highlighted split layer fabrication process after S/D formation. c) Optical microscopy image of the fabricated device. d) Cross-sectional and enlarged scanning electron microscopy (SEM) images of the fabricated device.

Results

We used a conventional, inverted staggered structure with an etched back channel; full photolithography was conducted for fabrication. The top contact (Cu) served as the source/drain (S/D) electrode, defined by chemical wet etching (Fig. 1a). We fabricated two types of devices after the formation of S/D, the split layers are highlighted in Figure 1b. Equivalent processing variables such as precursor, gas flow rate, power, pressure, and temperature were applied during the formation of the defect control layer (DCL) and passivation (PAS) layer. The fabricated TFTs had a length (L) of 7 μm and a width (W) of 4 μm (Fig. 1c). Figure 1d presents a cross-sectional view of the pristine device.

To optimize the SiO_x double-layer, we varied temperature, pressure, thickness, and annealing time while maintaining a total thickness of 200 nm for W/L = 4/7 μm to ensure desired switching behavior. To mitigate the impact of a thinner DCL on V_t_h (which becomes positive when DCL thickness is <80 nm), we used a 50 nm-thick DCL. The proposed device allowed for additional thermal treatments due to the sequential deposition process. Four cases were examined (no anneal, once at DCL, once at PAS, twice at PAS and DCL), revealing that annealing at the DCL improved V_t_h uniformity, while degradation was observed when annealing was performed at the PAS layer. This suggests that annealing at PAS may not effectively alleviate damage to the back channel due to impurities and/or defects. Therefore, annealing was only performed after DCL placement to achieve a positive V_t_h and good uniformity.

We examined the transfer characteristics of the proposed device as a function of the SiO_x formation method, i.e. after wet etched, pristine device, and proposed device. Initially, the V_t_h was extremely negative after S/D patterning, and switching behavior was not observed. However, subsequent dielectric formation enabled switching characteristics. Remarkably, the effect of the DCL on device-to-device uniformity was evident, as devices with nine TFTs showed negligible leakage current under negative gate-to-source voltage (V_GS) and uniform V_t_h distribution. The sequential formation of SiO_x with appropriate thermal annealing in the proposed device resulted in increased and uniform V_t_h, indicating effective repair of backchannel damage and improved device stability. The increased V_t_h and improved subthreshold gate swing (S.S.) of the proposed device suggest reduced oxygen deficiency and carrier/defect generation. The average S.S. values of the pristine and proposed devices were 0.53 and 0.46 V dec⁻¹, respectively. The larger trap density remaining in the pristine device compared to the proposed device, mainly due to the fabrication process of the SiO_x layer formation upon the IGZO, contributed to the higher S.S. value in the pristine device.

Both the L_CH-Dependent V_t_h range and the short-channel capability were drastically enhanced in the proposed device. A substantial difference emerged when L_CH What < 7 μm. In the pristine device, the V_t_h became increasingly negative as the L_CH became shorter and was extremely negative (<−5 V) at an L_CH of 5 μm. Finally, all switching was lost at an L_CH of 4 μm. In contrast, the V_t_h of the proposed device always had a positive value, and even the device with an L_CH of 4 μm maintained appropriate switching.

The transfer characteristics facilitate simple DIBL quantification; the change in V_t_h is divided by the applied drain bias difference (V_DS = 0.1, 10 V) [2,3]. Notably, this falls substantially from 177 in the pristine device to 84 mV V⁻¹ in the proposed device, at an L_CH of 5 μm. Because only appropriate switching characteristics at L_CH < 5 μm were observed in the proposed device, the actual difference becomes more serious at shorter L_CH. Thus, the proposed device is less sensitive than the pristine device to drain bias, even at L_CH <5 μm.

Throughout the conduction path, the total equivalent resistance of a transistor is composed of channel resistance (R_CH) and parasitic resistance (R₀) (series and contact resistances). As the L_CH decreases, the R_CH decreases and the remaining R₀ is the limiting factor in terms of short-channel device capability [4]. Thus, it appears that the total equivalent resistance and the effective channel of the proposed device are different from that of the pristine device. Besides, both devices commonly exhibited increased μ_FE as decreasing L_CH. The proposed method for forming the device with DCL appears to influence the channel configuration. Furthermore, in a short-channel device, the portion of L_CH that makes the greatest contribution to the gate bias dependency should be considered when estimating device mobility [5]. Thus, it is better to compare effective length-based mobilities (μ_FE _L_e_ff) that consider the effective channel length (L_e_ff).

To validate our assumptions and clarify the detailed geometry of L_CH, we conducted calculations of total resistance using the transmission line method (TLM). The results showed that the region of conducting behavior in the pristine device was sufficiently long, indicating high conductivity below 4 μm. In contrast, the region of conducting behavior in the proposed device was shorter, at ≈2.9 μm, and the resistance (R₀) was slightly increased. This reduced region of conducting behavior suggests a longer L_e_ff in the proposed device, with a larger proportion of L_e_ff within the L_CH, allowing for switching despite the shorter channel length (4 μm). The results showed that the proposed method with DCL mainly affects V_t_h rather than device mobility as the L_CH decreases.

From transmission electron microscopy and energy-dispersive X-ray spectroscopy, we have found that the DCL supplies oxygen to the oxygen-deficient back channel, filters inter-diffused hydrogen, and boosts out-diffusion of residual Cuⁿ⁺ from the back channel (Fig. 2a–c). Although these crucial functions were partly provided by the pristine PAS as a single layer, they were greatly enhanced by our method as a double layer with DCL, affording stable electrical characteristics even in short channels. Our process-dependent investigations revealed how the damaged IGZO recovered. As IGZO defects were thus controlled, the backchannel properties noticeably improved. Current flow in the back channel was confined, effectively redefining the channel (Fig. 2d).

Figure 2. a) Back-channel properties after wet etching, b) Improved copper... — Figure 2. a) Back-channel properties after wet etching, b) Improved copper out-diffusion by lower repulsive charges in DCL after DCL formation, c) Hydrogen filtering by interface trap and reduced pinhole in DCL after the formation of DCL and PAS. d) Comparisons of the finalized lattice structure of IGZO and channel configuration of tested devices.

Conclusion

We proposed a fabrication method to address V_t_h non-uniformity in downscaled devices. By sequentially forming a double-layered dielectric of homogeneous SiO_x at the back channel, we achieved advanced functionality compared to conventional materials. The DCL greatly improved the electrical characteristics of back-channel wet-etched IGZO TFTs, enabling consistent V_t_h values as L_CH decreased from 20 to 4 μm. The poor performance of short L_CH devices, caused by back-channel defects from wet etching and SiO_x deposition, was effectively recovered by the DCL. Additionally, the effective L_CH was increased by reducing the region of conducting behavior, allowing for appropriate switching even at 4 μm L_CH with superior performance. Furthermore, the proposed device exhibited a dramatically reduced V_t_h Range AS L_CH varied from 20 to 4 μm, thanks to the multi-functional DCL.

References

[1] Kyung K.M. et al. (2023). Suppressing Undesired Channel Length-Dependent Electrical Characteristics of Fully Integrated InGaZnO Thin-Film Transistors via Defect Control Layer. Adv. Electron. Mater. DOI.10.1002/aelm.202200986

[2] Raja, J. et al. (2014). Drain-induced barrier lowering and parasitic resistance induced instabilities in short-channel InSnZnO TFTs. IEEE Electron Device Letters. DOI: 10.1109/LED.2014.2318754.

[3] Kim, S.C. et al. (2015). Short channel amorphous In–Ga–Zn–O thin-film transistor arrays for ultra-high definition active matrix liquid crystal displays: Electrical properties and stability. Solid-State Electronics. DOI: 10.1016/J.SSE.2015.05.002.

[4] Zhao, Y. et al. (2020). High Performance Indium-Gallium-Zinc Oxide Thin Film Transistor via Interface Engineering. Advanced Functional Materials. DOI: 10.1002/ADFM.202003285.

[5] Kim, H.W. et al. (2018). Influence of effective channel length in self-aligned coplanar amorphous-indium-gallium-zinc-oxide thin-film transistors with different annealing temperatures. Applied Physics Letters. DOI: 10.1063/1.5027373.

Source: Image: Kyung, K.M.